1. Field of the Invention
The present invention relates to high-performance sampling and interleaving stages for high-speed analog-to-digital converters, in particular, for analog-to-digital converters operating at sampling frequencies of several tens of GS/s.
2. Description of the Related Art
Analog-to-digital converters (ADCs) can be implemented with different topologies. Technological restrictions, however, generally require interleaving of the input signal for high-speed ADCs, in particular at sampling rates beyond 20 GS/s. Due to the high requirements on bandwidth, precision and speed, sampling stages are often implemented in semiconductor processes such as SiGe or other high-performance processes. In order to achieve full system integration, the ADC preferably has to be fully integrated on a CMOS chip, which means that the interleaving and sampling stage has to be implemented in CMOS as well.
ADCs of this kind usually have a sampling and interleaving stage for receiving and distributing the input signal to be converted. The sampling and interleaving stage is therefore substantial for the performance of the ADC and is particularly responsive for bandwidth linearity and noise.
In an interleaved ADC, there generally is an ADC sub-stage in which the voltage of the input signal is stored on a capacitor. The ADC sub-stages are then connected to the capacitor of the sampling and interleaving stage by means of a buffer. The buffer must provide high linearity, low power and very high speed in order to enable high sampling bandwidths. The sampling and interleaving stage directly receives the input signal and is responsible for providing the input signal to the respective capacitor with a high linearity and high bandwidth and should further allow for a good skew calibration at low jitter.
U.S. Pat. No. 8,350,743 B2 discloses a sample-and-hold circuit, an analog-to-digital converter and switches that enable selectable ones of the outputs of a differential amplifier in the sample-and-hold circuit to be coupled to a circuit node of the analog-to-digital converter. The switches can be controlled such that the output of the differential amplifier can be reset without requiring an additional switch between the outputs of the differential amplifier.
U.S. Patent Application Publication No. 2013/0015990 A1 discloses a track-and-hold architecture with a tunable bandwidth. A track-and-hold circuit architecture is provided that uses a variation of the gate voltage of a sampling switch to vary the ON resistance of the sampling switch and thus change the bandwidth of the track-and-hold circuit to precisely match the bandwidth.
U.S. Pat. No. 8,248,289 B2 discloses track-and-hold circuits as parts of an analog-to-digital converter. By means of a multiplexer controlled by a clocking circuit the coupling between each of the track-and-hold circuits and the analog-to-digital converter is controlled.
European Patent No. 2,347,509 B1 discloses a time-interleaved analog-to-digital converter, wherein a track-and-hold unit is used for supplying the input signals to each of a plurality of analog-to-digital converting elements. The track-and-hold units to supply the input signal to one or more of the analog-to-digital converting elements have an improved linearity and can be fully implemented in CMOS technology.
U.S. Patent Application Publication No. 2012/0309337 A1 discloses a multi-layer interleaved analog-to-digital converter for receiving radio frequency signals.
U.S. Patent Application Publication No. 2010/0253414 A1 discloses a device for sampling a current signal in high-speed applications, in particular for use in analog-to-digital converting circuitries.
Van der Plas, G. et al., “A 0.16PJ/CONVERSION-STEP 2.5 MW 1.25GS/S 4 B ADC IN A 90 NM DIGITAL CMOS PROCESS”, Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, Feb. 6-9, 2006, discloses a high-speed ADC in CMOS that uses a dynamic offset-compensation scheme in its comparators.
Wei-Hsuan Tu et al., “A 1.2V 30 MW 8 B 800 MS/S TIME-INTERLEAVED ADC IN 65 NM CMOS”, IEEE Symposium on VLSI Circuits, 2008 Author(s): Pages 72-73, is related to a time-interleaved pipeline ADC high-speed input. It shows sub-ADC preamp sharing and reference voltage buffer current-reusing to minimize power consumption.
Furthermore, Alpman, E., “A 1.1V 50 MW 2.5GS/S 7 B TIME-INTERLEAVED C-2C SAR ADC IN 45 NM LP DIGITAL CMOS”, Solid-State Circuits Conference—Digest of Technical Papers, 2009, ISSCC 2009, IEEE International, Feb. 8-12, 2009, pages 76-77, 77a, discloses a time-interleaved successive approximation register-based (SAR) ADC that achieves high performance by using a small-area C-2C SAR architecture with low input capacitance, high-speed boosted switches to overcome a high device threshold, background comparator offset calibration and radix calibration; and redundant-ADC-based gain, offset and timing calibration to reduce errors.
Moreover, Verbruggen, B., “A 2.6 MW 6 B 2.2GS/S 4-TIMES INTERLEAVED FULLY DYNAMIC PIPELINED ADC IN 40 NM DIGITAL CMOS”, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, Feb. 7-11, 2010, pages 296-297, is related to a 2.2 GS/s interleaved ADC in CMOS, wherein each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. Threshold calibration corrects for amplifier and comparator imperfections.
Tousi, Y. M. et al., “A MINIATURE 2 MW 4 BIT 1.2 GS/S DELAY-LINE-BASED ADC IN 65 NM CMOS”, IEEE Journal of Solid-State Circuits, October 2011, Volume: 46, Issue 10, pages 2312-2325, describes a delay line-based analog-to-digital converter for high-speed applications. The ADC converts the sampled input voltage to a delay that controls the propagation velocity of a digital pulse. The output digital code is generated based on the propagation length of the pulse in a fixed time window.